Embedded Systems

Introduction High-resolution filtering at full sampling rates can be computationally expensive. Multi-rate DSP techniques allow engineers to: downsample signals apply narrowband suppression efficiently reduce computational load This approach is particularly useful in embedded and real-time systems. Why Multi-Rate Helps If interference occupies a narrow frequency band: full-rate processing wastes resources decimation reduces bandwidth narrower filters become cheaper Multi-rate strategies exploit spectral structure for efficiency. Practical Workflow A typical pipeline: Band-limit signal Downsample Apply narrowband suppression Upsample if necessary This reduces both complexity and latency. ...

Introduction In fixed-point DSP systems, IIR filters may exhibit persistent oscillations even when the input signal is zero. This phenomenon, known as a limit cycle, is caused by finite word-length effects and nonlinear quantization behavior. Unlike floating-point simulations, fixed-point arithmetic introduces rounding and saturation effects that can sustain artificial oscillations indefinitely. Why Limit Cycles Occur In IIR structures: feedback paths amplify quantization error rounding behaves nonlinearly zero-input does not guarantee zero-output Small residual quantization noise becomes trapped in feedback loops. ...

Introduction FIR and IIR filters both appear stable in textbook theory. In embedded DSP systems, their real-world behavior can be dramatically different. Engineers frequently discover that designs which simulate perfectly become unstable, noisy, or fragile once deployed. This article explains the practical stability differences between FIR and IIR filters under real numerical constraints. Theoretical Stability vs Practical Stability Mathematically: FIR filters are always stable IIR filters are stable if poles remain inside the unit circle Numerically: ...

Introduction In real-time DSP systems, filter design is not purely a frequency-domain problem. Every additional tap, pole, or processing stage introduces computational cost and delay. Engineers frequently face questions such as: Why does a sharper filter increase system latency? When does FIR linear phase become impractical? How many notches are safe in real-time pipelines? When should I prefer IIR over FIR? This article explains the tradeoffs between latency, filter complexity, and stability in practical DSP systems. ...